File:IDT79R3052Eb.jpg
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Summary
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| Description |
English: The IDT IDT79R3051 family is a series of high-performance 32-bit microprocessors featuring a high level of integration which are targeted to high-performance, but cost sensitive embedded processing applications. The IDT79R3051 family is designed to bring the high-performance inherent in the MIPS RISC architecture into low-cost, simplified, power sensitive applications.
Functional units were integrated onto the CPU core in order to reduce the total system cost, without significantly degrading system performance. Thus, the IDT79R3051 family is able to offer 35MIPS of integer performance at 40MHz without requiring external SRAM or caches. Furthermore, the IDT79R3051 family brings dramatic power reduction to these embedded applications, allowing the use of low-cost packaging for devices up to 25 MHz. The IDT79R3051 family allows customer applications to bring maximum performance at minimum cost. The IDT79R3051 family could be viewed as the embodiment of a discrete solution built around the IDT79R3000A or IDT79R3001. However, by integrating this functionality on a single chip, dramatic cost and power reductions are achieved. The IDT79R3052"E" incorporates 8kB of Instruction Cache, and features a full-function Memory Management Unit (MMU), including a 64-entry fully-associative Translation Lookaside Buffer (TLB). This is the same MMU incorporated into the IDT79R3000A and IDT79R3001. Die size: 7.0 x 5.2 mm |
| Date | |
| Source | Own work |
| Author | Antoinebercovici |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
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| current | 15:29, 21 April 2014 | | 4,981 × 3,847 (14.78 MB) | Antoinebercovici (talk | contribs) | User created page with UploadWizard |
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