File:2016 3 5 DeJitterizer with parallel processing.png

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2016_3_5_DeJitterizer_with_parallel_processing.png (673 × 496 pixels, file size: 76 KB, MIME type: image/png)

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English: A de-jitterizer node can take advantage of the need to process the received data in parallel inside the equipment. The SERDES halves needed for the conversion to and from parallel, can be exploited also the reduce the speed of some critical circuits of CDR2.

The figure shows the architecture as far as the two CDRs are involved, and makes evident the clocks at reduced( = 1/N) speed

CK1 (as well as CK1/ N ) may jitter almost up to +/- (SERDES / 2) and CK2/ N would still be able and eliminate such jitter.

The only circuits that operate at line speed are:

  • CDR1
  • The two shift registers, DESER and SER
  • The VCO of CDR2.

CDR2 uses a reduced speed phase comparator, but a VCO at line speed, to generate CK1 and, by division, CK1/ N.

Alternatively, the VCO of CDR2 could operate at reduced speed and CK1 could be synthesized from it.

The range of the comparator of CDR2 is +/- πN/2, i.e. N/2 U.I. .
Date
Source Own work
Author BORGATO Pierandrea

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Date/TimeThumbnailDimensionsUserComment
current11:10, 7 March 2016Thumbnail for version as of 11:10, 7 March 2016673 × 496 (76 KB)BORGATO Pierandrea (talk | contribs)Added connection from CDR2 to CK2/N~~~~
18:17, 5 March 2016Thumbnail for version as of 18:17, 5 March 2016673 × 496 (76 KB)BORGATO Pierandrea (talk | contribs)User created page with UploadWizard

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